876784 Intel, 876784 Datasheet - Page 714

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

19.1.19
714
HDCTL—Intel
(Intel
Address Offset: 40h
Default Value:
7:4
Bit
3
2
1
0
Reserved.
BITCLK Detect Clear (CLKDETCLR) — R/W.
0 = lock detect circuit is operational and maybe enabled.
1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains
NOTE: This bit is not affected by the D3
BITCLK Detect Enable (CLKDETEN) — R/W.
0 = Latches the current state of bit 1 (CLKDET#) in this register
1 = Enables the clock detection circuit
NOTE: This bit is not affected by the D3
BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.
It is set to 0 when the Intel
presence of an AC’97 codec on the link.
NOTES:
1.
2.
Intel
shared Intel High Definition Audio/AC ‘97 signals.
0 = AC ’97 mode is selected (Default)
1 = Intel High Definition Audio mode is selected
NOTES:
1.
2.
3.
®
High Definition Audio Controller—D27:F0)
clear when this bit is set to 1.
®
Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of
this bit and must be manipulated correctly in order to get a valid CLKDET#
indicator.
This bit is not affected by the D3HOT to D0 transition.
This bit has no effect on the visibility of the Intel High Definition Audio and AC
’97 function configuration space.
This bit is in the resume well and only clear on a power-on reset. Software must
not makes assumptions about the reset state of this bit and must set it
appropriately.
For the ICH7-U Ultra Mobile, this bit must be programmed to 1.
High Definition Audio/AC ‘97 Signal Mode — R/W. This bit selects the
00h
®
High Definition Audio Control Register
®
ICH7 detects that the BITCLK is toggling, indicating the
Intel® High Definition Audio Controller Registers (D27:F0)
Description
HOT
HOT
Attribute:
Size:
to D0 transition.
to D0 transition.
Intel
R/W, RO
8 bits
®
ICH7 Family Datasheet