876784 Intel, 876784 Datasheet - Page 538

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

12.3.2.8
12.3.2.9
538
PxTFD—Port [3:0] Task File Data Register (D31:F2)
Address Offset: Port 0: ABAR + 120h
Default Value:
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are:
D2H Register FIS
PIO Setup FIS
Set Device Bits FIS
PxSIG—Port [3:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h
Default Value:
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
31:16
15:8
31:0
7:0
Bit
Bit
Reserved
Error (ERR) — RO. Contains the latest copy of the task file error register.
Status (STS) — RO. Contains the latest copy of the task file status register. Fields of
note in this register that affect AHCI.
Signature (SIG) — RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
31:24
23:16
15:8
6:4
2:1
7:0
Bit
Bit
7
3
0
Port 1: ABAR + 1A0h (ICH7R and ICH7DH Only)
Port 2: ABAR + 220h
Port 3: ABAR + 2A0h (ICH7R and ICH7DH Only)
0000007Fh
Port 1: ABAR + 1A4h (ICH7R and ICH7DH Only)
Port 2: ABAR + 224h
Port 3: ABAR + 2A4h (ICH7R and ICH7DH Only)
FFFFFFFFh
Field
LBA High Register
LBA Mid Register
LBA Low Register
Sector Count Register
Field
DRQ
BSY
ERR
N/A
N/A
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Definition
Indicates the interface is busy
Not applicable
Indicates a data transfer is
requested
Not applicable
Indicates an error during the
transfer
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
RO
32 bits
RO
32 bits
®
ICH7 Family Datasheet