876784 Intel, 876784 Datasheet - Page 517

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.43
Intel
®
ICH7 Family Datasheet
BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h
Default Value:
(Desktop
(Desktop
(Mobile
31:14
Only)
Only)
Only)
Bits
13
13
12
11
10
9
Reserved
Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit
field, the Intel
parameters specified in this register and the data specified in BFTD1 and BFTD2. The
BIST FIS will only be initiated if a device on Port 3 is present and ready (not partial/
slumber state). After a BIST FIS is successfully completed, software must disable and
re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the ICH7 to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Reserved.
Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit
field, the ICH7 initiates a BIST FIS to the device on Port 2, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device on Port 2 is present and ready (not partial/slumber state).
After a BIST FIS is successfully completed, software must disable and re-enable the
port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to
return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P2BFI bit
to initiate another BIST FIS. This can be retried until the BIST FIS eventually
completes successfully
BIST FIS Successful (BFS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = BIST FIS transmitted by ICH7 received an R_OK completion status from the
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = BIST FIS transmitted by ICH7 received an R_ERR completion status from the
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit
field, the ICH7 initiates a BIST FIS to the device on Port 1, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device on Port 1 is present and ready (not partial/slumber state).
After a BIST FIS is successfully completed, software must disable and re-enable the
port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to
return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P1BFI bit
to initiate another BIST FIS. This can be retried until the BIST FIS eventually
completes successfully
device.
device.
00000000h
–
E3h
®
ICH7 initiates a BIST FIS to the device on Port 3, using the
Description
Attribute:
Size:
R/W, R/WC
32 bits
517