876784 Intel, 876784 Datasheet - Page 692

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

692
23:21
20:18
17:15
14:8
6:2
Bit
24
7
1
0
BME Receive Check Enable (BMERCE) — R/W.
0 = Disable.
1 = Enable. Receive transaction layer will treat the TLP as an Unsupported Request
NOTE: Messages, IO, Configuration, and Completions are not checked for BME.
Reserved
Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit
Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/
F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by
BIOS.
Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit
Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/
F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden
by BIOS.
Reserved
Port I/OxApic Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
Reserved
Hot Plug SMI Enable (HPME) — R/W.
0 = Disable. SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
Power Management SMI Enable (PMME) — R/W.
0 = Disable. SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is
Port #
error if a memory read or write request is received and the Bus Master Enable bit is
not set.
detected.
1
2
3
4
5
6
Address
FEC1_0000h – FEC1_7FFFh
FEC1_8000h – FEC1_FFFFh
FEC2_0000h – FEC2_7FFFh
FEC2_8000h – FEC2_FFFFh
FEC3_0000h – FEC3_7FFFh
FEC3_8000h – FEC3_FFFFh
PCI Express* Configuration Registers (Desktop and Mobile Only)
Description
Intel
®
ICH7 Family Datasheet