876784 Intel, 876784 Datasheet - Page 668

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

18.1.4
668
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 06h
Default Value:
10:9
Bit
Bit
15
14
13
12
11
5
4
3
2
1
0
VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.
Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base
Specification.
Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.
Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI
Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1 = Enable. Allows memory cycles within the range specified by the memory base and
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Root port received a command or data from the backbone with a parity error. This
Signaled System Error (SSE) — R/WC.
0 = No system error signaled.
1 = Root port signaled a system error to the internal SERR# logic.
Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the
1 = Root port received a completion with unsupported request status from the
Received Target Abort (RTA) — R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Root port received a completion with completer abort from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
1 = Root port forwarded a target abort received from the downstream device onto the
DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base
Specification.
Express* device.
registers are master aborted on the backbone.
limit registers can be forwarded to the PCI Express device.
are master aborted on the backbone.
registers can be forwarded to the PCI Express device.
is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
backbone.
backbone.
backbone.
0010h
–
07h
PCI Express* Configuration Registers (Desktop and Mobile Only)
Description
Description
Attribute:
Size:
Intel
R/WC, RO
16 bits
®
ICH7 Family Datasheet