876784 Intel, 876784 Datasheet - Page 427

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.1.7
10.8.1.8
Intel
®
ICH7 Family Datasheet
MSC_FUN—Miscellaneous Functionality Register
(PM—D31:F0)
Offset Address: ADh
Default Value:
Power Well:
EL_STS—Intel
D31:F0) (ICH7DH Only)
Offset Address: B0h
Default Value:
Power Well:
7:5
Bit
Bit
7:2
1:0
4
3
2
1
0
Reserved
EL_SCI_NOW_STS— R/WC: This bit goes active when software writes a 1 to
EL_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the Intel
Quick Resume Technology (QRT) software to transition the reaction to an Intel QRT
event from an SMI# handler to an SCI handler. This bit remains set until a 1 is written
to this bit position.
Once a 1 is written to this bit position, the logic will “re-arm” to allow the bit to be set
on the next write of 1 to SCI_NOW_CNT (Offset B1h:Bit 8).
EL_PB_SCI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high-to-low (post-debounce). It can be enabled to cause an SCI that will allow the
Intel QRT software to see when the power button has been pressed. It is a separate bit
from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide
any indication to other (i.e. Intel QRT) software.
The Intel QRT software clears EL_PB_SCI_STS by writing a 1 to this bit position.
Reserved
EL_PB_SMI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high-to-low (post-debounce). It can be enabled to cause an SMI# that will allow the
Intel QRT software to see when the power button has been pressed. It is a separate bit
from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide
any indication to other (i.e., Intel QRT) software.
The Intel QRT software clears EL_PB_SMI_STS by writing a 1 to this bit position.
Reserved.
Reserved
USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short Single-
Ended Zero (SE0) condition on the USB ports from being interpreted by the UHCI host
controller as a disconnect. BIOS should set to 11b.
®
00h
Resume
00h
Resume
Quick Resume Technology Status Register (PM—
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8-bit
R/WC, RO
8-bit
427