876784 Intel, 876784 Datasheet - Page 616

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

15.2.2
616
BMISP—Bus Master IDE Status Register (IDE—D31:F1)
Address Offset: BMIBASE + 02h
Default Value:
(Desktop
Mobile
Mobile
Bit
(Ultra
Only)
Only)
0
and
4:3
Bit
7
6
6
5
Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot
1 = Enables bus master operation of the controller. Bus master operation does not
NOTE: This bit is intended to be cleared by software after the data transfer is
PRD Interrupt Status (PRDIS) — R/WC.
0 = When this bit is cleared by software, the interrupt is cleared.
1 = Set when the host controller completes execution of a PRD that has its Interrupt
Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
Reserved
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
Reserved. Returns 0.
be stopped and then resumed. If this bit is reset while bus master operation is still
active (i.e., the Bus Master IDE Active bit (BMIBASE + 02h, bit 0) of the Bus Master
IDE Status register for that IDE channel is set) and the drive has not yet finished
its data transfer (the Interrupt bit (BMIBASE + 02h, bit 2) in the Bus Master IDE
Status register for that IDE channel is not set), the bus master command is said to
be aborted and data transferred from the drive may be discarded instead of being
written to system memory.
actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI
configuration space is also set. Bus master operation begins when this bit is
detected changing from 0 to 1. The controller will transfer data between the IDE
device and memory only when this bit is set. Master operation can be halted by
writing a 0 to this bit.
bit (bit 2 of this register) set.
drive 1 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The Intel
It is intended for systems that do not attach BMIDE to the PCI bus.
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The ICH7 does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically.
00h
Description
Description
Attribute:
Size:
IDE Controller Registers (D31:F1)
®
Intel
ICH7 does not use this bit.
R/W, R/WC
8 bits
®
ICH7 Family Datasheet