876784 Intel, 876784 Datasheet - Page 120

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

5.5.1.3
Table 5-7.
5.5.1.4
Table 5-8.
120
Cycle Type / Direction (CYCTYPE + DIR)
The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0.
Cycle Type Bit Definitions
NOTE: All other encodings are RESERVED.
SIZE
Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits.
Bits[1:0] are encoded as listed in
Transfer Size Bit Definition
Bits[3:2]
Bits[1:0]
00
00
10
10
11
00
01
10
11
Bit1
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
running a bus master cycle drives this combination, the ICH7 may abort the
transfer.
32-bit transfer (4 bytes)
0
1
0
1
x
Table 5-7
I/O Read
I/O Write
Desktop and Mobile: DMA Read
Ultra Mobile: Reserved
Desktop and Mobile: DMA Write
Ultra Mobile: Reserved
Reserved. If a peripheral performing a bus master cycle generates this
value, the Intel
shows the valid bit encodings.
®
ICH7 does not drive this combination. If a peripheral
Table
®
ICH7 aborts the cycle.
5-8.
Size
Definition
Intel
®
ICH7 Family Datasheet
Functional Description