876784 Intel, 876784 Datasheet - Page 691

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.44
Intel
®
ICH7 Family Datasheet
MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: D8h
Default Value:
1:0
Bit
Bit
31
30
29
28
27
26
25
Power Management SCI Enable (PMCE) — R/W.
0 = Disable. SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is
Hot Plug SCI Enable (HPCE) — R/W.
0 = Disable. SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Link Hold Off (LHO)— R/W.
0 = Not in Link Hold Off.
1 = The port will not take any TLP. This is used during loopback mode to fill up the
Address Translator Enable (ATE) — R/W. This bit is used to enable address
translation via the AT bits in this register during loopback mode.
0 = Disable.
1 = Enable.
Reserved.
Invalid Receive Bus Number Check Enable (IRBNCE) — R/W.
0 = Disable.
1 = Enable. Receive transaction layer will signal an error if the bus number of a Memory
NOTE: Messages, IO, Configuration, and Completions are not checked for valid bus
Invalid Receive Range Check Enable (IRRCE) — R/W.
0 = Disable.
1 = Enable. Receive transaction layer will treat the TLP as an Unsupported Request
NOTE: Messages, I/O, Configuration, and Completions are not checked for valid
Power State (PS) — R/W. This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3
NOTE: When in the D3
detected.
downstream queue.
request does not fall within the range between SCBN and SBBN. If this check is
enabled and the request is a memory write, it is treated as an Unsupported
Request. If this check is enabled and the request is a non-posted memory read
request, the request is considered a Malformed TLP and a fatal error.
error if the address range of a memory request does not outside the range between
prefetchable and non-prefetchable base and limit.
number.
address ranges.
the I/O and memory spaces are not. Type 1 configuration cycles are also not
accepted. Interrupts are not required to be blocked as software will disable
interrupts prior to placing the port into D3HOT. If software attempts to write a
‘10’ or ‘01’ to these bits, the write will be ignored.
HOT
00110000h
state
–
DBh
HOT
state, the controller’s configuration space is available, but
Description
Description
Attribute:
Size:
R/W
32 bits
691