876784 Intel, 876784 Datasheet - Page 553

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
13.1.19
Intel
®
ICH7 Family Datasheet
NOTES:
1.
2.
PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F7)
Address Offset: 54h
Default Value:
14:13
12:9
7:2
2:0
Bit
Bit
15
4
3
8
Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the ICH7 is used, bits 15:11 and 8:6 in this register are writable when the
WRT_RDONLY bit (D29:F7:80h, bit 0) is set. The value written to this register does not
affect the hardware other than changing the value returned during a read.
Reset: core well, but not D3-to-D0 warm reset.
PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if
1 = This bit is set when the Intel
NOTE: This bit must be explicitly cleared by the operating system each time the
Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data
register.
Data Select — RO. Hardwired to 0000b indicating it does not support the associated
Data register.
PME Enable — R/W.
0 = Disable.
1 = Enable. Enables ICH7 EHC to generate an internal PME signal when PME_Status is
NOTE: This bit must be explicitly cleared by the operating system each time it is
Reserved
Reserved
PME Clock (PME_CLK) — R/W (special). The ICH7 reports 0, indicating that no PCI
clock is required to generate PME#.
Version (VER) — R/W (special). The ICH7 reports 010b, indicating that it complies
with Revision 1.1 of the PCI Power Management Specification.
enabled).
independent of the state of the PME_En bit.
1.
operating system is loaded.
initially loaded.
0000h
–
55h
®
ICH7 EHC would normally assert the PME# signal
Description
Description
Attribute:
Size:
R/W, R/WC, RO
16 bits
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