876784 Intel, 876784 Datasheet - Page 227

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
Note:
Note:
5.21.7.1
Note:
Table 5-54. Slave Write Registers
Intel
®
ICH7 Family Datasheet
The external microcontroller should not attempt to access the ICH7’s SMBus slave logic
until either:
The 800 ms case is based on the scenario where the RTC Battery is dead or missing
such that the RTC Power Well comes up simultaneously with Suspend Well. In this case,
the RTC clock may take a while to stabilize. The ICH7 uses the RTC clock to extend the
internal RSMRST# by ~100 ms. Therefore, if the clock is slow to toggle, this time could
be extended. 800 ms is assumed to be sufficient guardband for this.
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, the ICH7 slave logic's behavior is undefined. This is interpreted
as an unexpected idle and should be avoided when performing management activities
to the slave logic.
When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if the ICH7 slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH7 SMBus Slave I/F. The
“Command” field (bits 11
(bits 20
If the ICH7 is sent a ‘Hard Reset Without Cycling’ command on SMBus while the system
is in S4 or S5, the reset command will not be executed until the next wake event.
SMBus write commands sent after the Hard Reset Without Cycling command and
before the wake event will be NAKed by the ICH7. This also applies to any SMBus wake
commands sent after a Hard Reset Without Cycling command, such that the SMBus
wake command will not cause the system to wake. Any SMBus read that is accepted by
the ICH7 will complete normally. Intel
impacted as Intel AMT does not use the Hard Reset Without Cycling command while the
system is in S4 or S5.
Table 5-54
NOTE: The external microcontroller is responsible to make sure that it does not update the
• 800 milliseconds after both: RTEST# is high and RSMRST# is high, OR
• the PLTRST# de-asserts
Register
9–FFh
1–3
6–7
0
4
5
8
contents of the data byte registers until they have been read by the system processor. The
ICH7 overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. ICH7
will not attempt to cover this race condition (i.e., unpredictable results in this case).
:
27) indicate the value that should be written to that register.
has the values associated with the registers.
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
:
18) indicate which register is being accessed. The Data field
Table 5-55
®
Active Management Technology is not
below for legal values written to this register.
Function
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