876784 Intel, 876784 Datasheet - Page 369

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.1.14
10.1.15
Intel
®
ICH7 Family Datasheet
ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Default Value:
Lockable:
GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh
Default Value:
31:16
15:6
6:3
2:0
5:1
Bit
Bit
7
0
ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be
Reserved. Always 0.
Base Address (BA) — R/W. Provides the 64 bytes of I/O space for GPIO.
Reserved. Always 0.
RO. Hardwired to 1 to indicate I/O space.
ACPI power management function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and are not affected by this bit.
000b
001b
010b
011b
100b
101b
110b
111b
Bits
programmed for active-high reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC should be programmed for active-low
00h
No
00000001h
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available if APIC enabled)
IRQ21 (Only available if APIC enabled)
IRQ22 (Only available if APIC enabled)
IRQ23 (Only available if APIC enabled)
Description
Description
Attribute:
Size:
Usage:
Power Well:
Attribute:
Size:
R/W
8 bit
ACPI, Legacy
Core
R/W, RO
32 bit
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