876784 Intel, 876784 Datasheet - Page 433

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH7 Family Datasheet
(Desktop
Mobile
Mobile
13:12
(Ultra
Only)
Only)
and
Bit
15
14
14
11
10
9
Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused
by a CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN
If the AFTERG3_EN bit is not set and a power failure (such as removed batteries on a
mobile/Ultra Mobile platform) occurs without the SLP_EN bit set, the system will
return to an S0 state when power returns, and the WAK_STS bit will not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit
having been set, the system will go into an S5 state when power returns, and a
subsequent wake event will cause the WAK_STS bit to be set. Note that any
subsequent wake event would have to be caused by either a Power Button press, or
an enabled wake event that was preserved through the power failure (enable bit in
the RTC well).
PCI Express Wake Status (PCIEXPWAK_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during
1 = This bit is set by hardware to indicate that the system woke due to a PCI Express
NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping
Reserved
Reserved
Power Button Override Status (PRBTNOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (i.e., the power button is
RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8#
Reserved
bit) and an enabled wake event occurs. Upon setting this bit, the Intel
transition the system to the ON state.
the write or the PME message received indication has not been cleared in the
root port, then the bit will remain active (i.e. all inputs to this bit are level-
sensitive).
wakeup event. This wakeup event can be caused by the PCI Express WAKE# pin
being active or receipt of a PCI Express PME message at a root port. This bit is
set only when one of these events causes the system to transition from a non-S0
system power state to the S0 system power state. This bit is set independent of
the state of the PCIEXP_WAKE_DIS bit.
pressed for at least 4 consecutive seconds), or due to the corresponding bit in
the SMBus slave message. The power button override causes an unconditional
transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI
handler clears this bit by writing a 1 to it. This bit is not affected by hard resets
via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved
through power failures. Note that if this bit is still asserted when the global
SCI_EN is set then an SCI will be generated.
signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting
of the RTC_STS bit will generate a wake event.
state. Thus, if the bit is 1 and the system is put into a sleeping state, the
system will not automatically wake.
Description
®
ICH7 will
433