876784 Intel, 876784 Datasheet - Page 621

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.3
Intel
®
ICH7 Family Datasheet
PCICMD—PCI Command Register (Audio—D30:F2)
Address Offset: 04h
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI 2.3 specification for complete
details on each bit.
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved. Read 0.
Interrupt Disable (ID) — R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. Controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — R/W. Enables memory space addresses to the AC ’97
Audio controller.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 Audio
controller I/O space registers.
0 = Disable (Default).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
NOTE: This bit becomes writable when the IOSE bit in offset 41h is set. If at any point
MSIs.
programmed prior to setting this bit.
software decides to clear the IOSE bit, software must first clear the IOS bit.
0000h
No
–
05h
Description
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
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