876784 Intel, 876784 Datasheet - Page 165

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 5-32. GPI Wake Events
5.14.7.4
5.14.7.5
Note:
Intel
®
ICH7 Family Datasheet
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space.
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to the ICH7 are
insignificant.
PCI Express* WAKE# Signal and PME Event Message (Desktop and
Mobile only)
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using
the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH7 will set the PCI_EXP_STS bit.
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
The ICH7 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
GPI[15:13,11:8]
GPI[12, 7:0]
(G3 state), the PWRBTN_STS bit is reset. When the ICH7 exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because V
standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
GPI
Table 5-32
Power Well
Resume
Core
summarizes the use of GPIs as wake events.
Wake From
S1–S5
S1
Compliant
Compliant
Notes
ACPI
ACPI
CC
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