876784 Intel, 876784 Datasheet - Page 493

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.5
12.1.6
12.1.6.1
Intel
®
ICH7 Family Datasheet
RID—Revision Identification Register (SATA—D31:F2)
Offset Address: 08h
Default Value:
PI—Programming Interface Register (SATA–D31:F2)
When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h
Address Offset: 09h
Default Value:
7:0
Bit
2:0
6:4
Bit
Bit
4
3
7
3
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities
list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
1 = Interrupt is to be asserted
Reserved
This read-only bit is a 1 to indicate that the ICH7 supports bus master operation
Reserved. Will always return 0.
Secondary Mode Native Capable (SNC) — RO.
0 = Secondary controller only supports legacy mode.
1 = Secondary controller supports both legacy and native modes.
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports
as a 0. When MAP.MV is 00b, this bit reports as a 1.
command register [offset 04h]).
See bit description
See bit description
®
Description
Description
Description
I/O Controller Hub 7 (ICH7) Family Specification
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, RO
8 bits
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