876784 Intel, 876784 Datasheet - Page 541

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.12
Intel
®
ICH7 Family Datasheet
PxSERR—Port [3:0] Serial ATA Error Register (D31:F2)
Address Offset: Port 0: ABAR + 130h
Default Value:
31:16
Bit
Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by
diagnostic software in validating correct operation or isolating failure modes:
Bits
31:27Reserved
26
25
24
23
22
21
20
19
18
17
16
received. This bit is reflected in the interrupt register PxIS.PCS.
the Transport layer with good CRC, but had a type field that was not recognized.
the transition from one state to another within the Transport layer since the last
time this bit was cleared.
conditions was encountered. The Link Layer state machine defines the conditions
under which the link layer detects an erroneous transition.
was received in response to frame transmission. Such errors may be the result of
a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or
other error condition leading to a negative handshake on a transmitted frame.
Layer.
errors occurred.
signal changed state since the last time this bit was cleared. In the Intel
this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of
this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will
be generated if enabled. Software clears this bit by writing a 1 to it.
Exchanged (X): When set to one this bit indicates a COMINIT signal was
Unrecognized FIS Type (F): Indicates that one or more FISs were received by
Transport state transition error (T): Indicates that an error has occurred in
Link Sequence Error (S): Indicates that one or more Link state machine error
Handshake Error (H): Indicates that one or more R_ERR handshake response
CRC Error (C): Indicates that one or more CRC errors occurred with the Link
Disparity Error (D): This field is not used by AHCI.
10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding
Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.
Phy Internal Error (I): Indicates that the Phy detected some internal error.
PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy
Description
Port 1: ABAR + 1B0h (
Port 2: ABAR + 230h
Port 3: ABAR + 2B0h (ICH7R and ICH7DH Only)
00000000h
I
CH7R and ICH7DH Only)
Description
Attribute:
Size:
R/WC
32 bits
®
ICH7,
541