876784 Intel, 876784 Datasheet - Page 246

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

5.25.3
5.25.3.1
Note:
5.25.3.2
246
SPI Device Compatibility Requirements
A variety of SPI flash devices exist in the market. In order for a SPI device to be
compatible with the ICH7 it must meet the minimum requirements detailed in the
following sections.
Intel
(Non-Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 in a non-shared flash configuration:
The ICH7 only supports Mode 0 on SPI flash devices
Intel
Configuration Requirements (Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 and the Intel PRO 82573E GbE with Intel AMT device in a shared flash
configuration:
The following are requirements that are in common with the BIOS only configuration
listed in
• Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB, 512
• Required command set and associated opcodes (Refer to
• Device identification command (Refer to
• Device must support multiple writes to a page without requiring a preceding erase
• Serial flash device must ignore the upper address bits such that an address of
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
• If the device receives a command that is not supported, the device must complete
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
• Minimum density of 4 Mb (Platform dependent based on size of BIOS).
• Required command set and associated opcodes (Refer to
• Device identification command (Refer to
• Device must support multiple writes to a page without requiring a preceding erase
• Serial flash device must ignore the upper address bits such that an address of
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
• If the device receives a command that is not supported, the device must complete
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
bytes, or 256 bytes.
cycle (Refer to
FFFFFFh simply aliases to the top of the flash memory.
edge of the clock).
the cycle gracefully without any impact on the flash content.
inside the designated area (page, sector, block, chip, or etc.).
cycle (Refer to
FFFFFFh simply aliases to the top of the flash memory.
edge of the clock).
the cycle gracefully without any impact on the flash content.
inside the designated area (page, sector, block, chip, or etc.).
®
®
ICH7 with Intel
ICH7 SPI Based BIOS Only Configuration Requirements
Section
5.25.3.1:
Section
Section
5.25.4.3)
5.25.4.3)
®
PRO 82573E with Intel AMT Firmware
Section
Section
5.25.4.2).
5.25.4.2)
Intel
Section
Section
®
ICH7 Family Datasheet
Functional Description
5.25.4.1).
5.25.4.1)