876784 Intel, 876784 Datasheet - Page 57

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Signal Description
2.6
Table 2-6.
Intel
®
ICH7 Family Datasheet
PCI Interface
PCI Interface Signals (Sheet 1 of 3)
C/BE[3:0]#
AD[31:0]
DEVSEL#
FRAME#
Name
IRDY#
Type
I/O
I/O
I/O
I/O
I/O
PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
address (32 bits). During subsequent clocks, AD[31:0] contain data. The
Intel
PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address phase
of a transaction, C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# define the Byte Enables.
All command encodings not shown are reserved. The ICH7 does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
Device Select: The ICH7 asserts DEVSEL# to claim a PCI transaction.
As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral
attempts an access to an internal ICH7 address or an address destined
DMI (main memory or graphics). As an input, DEVSEL# indicates the
response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is
tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-
stated by the ICH7 until driven by a target device.
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator asserts
FRAME#, data transfers continue. When the initiator negates FRAME#,
the transaction is in the final data phase. FRAME# is an input to the
ICH7 when the ICH7 is the target, and FRAME# is an output from the
ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the
ICH7 until driven by an initiator.
Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY#
indicates the ICH7 has valid data present on AD[31:0]. During a read, it
indicates the ICH7 is prepared to latch data. IRDY# is an input to the
ICH7 when the ICH7 is the target and an output from the ICH7 when the
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until driven by
an initiator.
C/BE[3:0]#
0000b
0001b
0010b
0011b
0110b
0111b
1010b
1011b
1100b
1110b
1111b
®
ICH7 will drive all 0s on AD[31:0] during the address phase of all
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
Description
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