876784 Intel, 876784 Datasheet - Page 442

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

442
Bit
9
8
7
6
PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
NOTES:
1.
2.
3.
4.
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can
independently cause an SMI# or SCI, so this bit does not need to do so (unlike the
other bits in this register). Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the ICH7’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the ICH7’s
NOTES:
1.
2.
3.
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = TOC logic did Not cause SCI.
1 = Set by hardware when the TCO logic causes an SCI.
• The PME event message was received on one or more of the PCI Express* ports (Desktop and
• An Assert PMEGPE message received from the (G)MCH via DMI
Mobile Only)
SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the
system is already awake. The SMI handler should then clear this bit.
The PCI WAKE# pin has no impact on this bit.
If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a
Deassert PMEGPE message must be received prior to the software write in
order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the
level-triggered SCI will remain active.
A race condition exists where the PCI Express device sends another PME
message because the PCI Express device was not serviced within the time
when it must resend the message. This may result in a spurious interrupt,
and this is comprehended and approved by the PCI Express* Specification,
Revision 1.0a. The window for this race condition is approximately
95–105 milliseconds.
This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the
system is in the S0 state. Therefore, to avoid an instant wake on subsequent
transitions to sleep states, software must clear this bit after each reception of
the Wake/SMI# command or just prior to entering the sleep state.
If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be
cleared by internal logic when a THRMTRIP# event happens or a Power
Button Override event. However, THRMTRIP# or Power Button Override event
will not clear SMB_WAK_STS if it is set due to SMBALERT# signal going
active.
The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by
software before the SMB_WAK_STS bit is cleared.
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH7 Family Datasheet