876784 Intel, 876784 Datasheet - Page 5

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Intel
®
5.6
5.7
5.8
5.9
5.10
ICH7 Family Datasheet
DMA Operation (D31:F0) .................................................................................. 124
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
LPC DMA (Desktop and Mobile Only) .................................................................. 127
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
8254 Timers (D31:F0) ..................................................................................... 130
5.8.1
5.8.2
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133
5.9.1
5.9.2
5.9.3
5.9.4
5.9.5
5.9.6
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140
5.10.1 Interrupt Handling................................................................................ 140
5.10.2 Interrupt Mapping ................................................................................ 140
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141
5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141
Channel Priority ................................................................................... 124
5.6.1.1
5.6.1.2
Address Compatibility Mode ................................................................... 125
Summary of DMA Transfer Sizes ............................................................. 125
5.6.3.1
Autoinitialize........................................................................................ 126
Software Commands............................................................................. 126
Asserting DMA Requests........................................................................ 127
Abandoning DMA Requests .................................................................... 127
General Flow of DMA Transfers ............................................................... 128
Terminal Count .................................................................................... 128
Verify Mode ......................................................................................... 128
DMA Request Deassertion...................................................................... 129
SYNC Field / LDRQ# Rules ..................................................................... 129
Timer Programming .............................................................................. 131
Reading from the Interval Timer............................................................. 132
5.8.2.1
5.8.2.2
5.8.2.3
Interrupt Handling................................................................................ 134
5.9.1.1
5.9.1.2
5.9.1.3
Initialization Command Words (ICWx) ..................................................... 135
5.9.2.1
5.9.2.2
5.9.2.3
5.9.2.4
Operation Command Words (OCW) ......................................................... 136
Modes of Operation .............................................................................. 136
5.9.4.1
5.9.4.2
5.9.4.3
5.9.4.4
5.9.4.5
5.9.4.6
5.9.4.7
5.9.4.8
5.9.4.9
5.9.4.10 Automatic End of Interrupt Mode .............................................. 138
Masking Interrupts ............................................................................... 139
5.9.5.1
5.9.5.2
Steering PCI Interrupts ......................................................................... 139
5.10.4.1 Edge-Triggered Operation......................................................... 142
Fixed Priority.......................................................................... 125
Rotating Priority ..................................................................... 125
Words ................................................................................... 126
Simple Read........................................................................... 132
Counter Latch Command.......................................................... 132
Read Back Command .............................................................. 132
Generating Interrupts.............................................................. 134
Acknowledging Interrupts ........................................................ 134
Hardware/Software Interrupt Sequence ..................................... 135
ICW1 .................................................................................... 135
ICW2 .................................................................................... 136
ICW3 .................................................................................... 136
ICW4 .................................................................................... 136
Fully Nested Mode................................................................... 136
Special Fully-Nested Mode........................................................ 137
Automatic Rotation Mode (Equal Priority Devices)........................ 137
Specific Rotation Mode (Specific Priority).................................... 137
Poll Mode ............................................................................... 137
Cascade Mode ........................................................................ 138
Edge and Level Triggered Mode................................................. 138
End of Interrupt (EOI) Operations ............................................. 138
Normal End of Interrupt........................................................... 138
Masking on an Individual Interrupt Request ................................ 139
Special Mask Mode.................................................................. 139
Address Shifting When Programmed for 16-Bit I/O Count by
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