876784 Intel, 876784 Datasheet - Page 368

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.1.11
10.1.12
10.1.13
368
SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch
Default Value:
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
CAPP—Capability List Pointer (LPC I/F—D31:F0)
Offset Address: 34h
Default Value:
PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h
Default Value:
Lockable:
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
31:16
15:0
31:16
7:0
Bit
Bit
15:7
6:1
Bit
0
Subsystem ID (SSID) — R/WO This is written by BIOS. No hardware action taken on
this value.
Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware action
taken on this value.
Capability Pointer (CP) — RO. Indicates the offset of the first item.
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
00000000h
E0h
00000001h
No
–
–
43h
2Fh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Usage:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
R/WO
32 bits
RO
8 bits
Core
R/W, RO
32 bit
ACPI, Legacy
Core
®
ICH7 Family Datasheet