876784 Intel, 876784 Datasheet - Page 547

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
13.1.3
Intel
®
ICH7 Family Datasheet
PCICMD—PCI Command Register
(USB EHCI—D29:F7)
Address Offset: 0h4
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit (D29:F7:06h, bit 3) is not affected by
the interrupt enable.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO.
1 = EHCI Host Controller will check for correct parity and halt operation when bad parity is detected
This bit must be set in order for the parity errors to generate SERR#.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the Intel
Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory
Space registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register
I/O Space Enable (IOSE) — RO. Hardwired to 0.
when it receive a completion status other than “successful” for one of its DMA-
initiated memory reads on DMI (and subsequently on its internal interface).
during the data phase as recommended by the EHCI specification. If it detects bad parity on
the address or command phases when this bit is set to 1, the host controller does not take the
cycle, halts the host controller (if currently not halted), and sets the host system error bit in the
USBSTS register. Note that this applies to both requests and completions from the system
interface.
(D29:F7:10h) for USB 2.0 should be programmed before this bit is set.
0000h
–
05h
®
ICH7 to act as a master on the PCI bus for USB transfers.
(
EHC) is capable of generating (internally) SERR#
Description
Attribute:
Size:
R/W, RO
16 bits
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