876784 Intel, 876784 Datasheet - Page 124

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

5.6
Note:
Figure 5-5.
5.6.1
124
DMA Operation (D31:F0)
For ICH7-U Ultra Mobile, LPC DMA is not supported.
The ICH7 supports LPC DMA using the ICH7’s DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is
configured using registers in the PCI configuration space. These registers allow
configuration of the channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with
seven independently programmable channels
corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to
channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Intel
Each DMA channel is hardwired to the compatible settings for DMA device size:
channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are
hardwired to 16-bit, count-by-words (address shifted) transfers.
ICH7 provides 24-bit addressing in compliance with the ISA-Compatible specification.
Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16
least-significant bits of the 24-bit address, an ISA-Compatible Page Register which
contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization
following a DMA termination.
Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3
and channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service can be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. See the detailed register description for Request Register
programming information in
®
ICH7 DMA Controller
Channel 1
Channel 2
Channel 3
Channel 0
Section
DMA-1
10.2.
Channel 4
Channel 5
Channel 6
Channel 7
(Figure
5-5). DMA controller 1 (DMA-1)
DMA-2
Intel
®
ICH7 Family Datasheet
Functional Description