876784 Intel, 876784 Datasheet - Page 276

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

7.1.30
7.1.31
276
ILCL—Internal Link Capabilities List Register
Offset Address: 01A0–01A3h
Default Value:
LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h
Default Value:
Desktop
Desktop
Mobile/
Mobile/
Mobile
Mobile
31:20
19:16
31:18
17:15
17:15
14:12
11:10
11:10
Ultra
Ultra
15:0
Only
Only
Only
Only
9:4
3:0
Bit
Bit
Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.
Capability Version (CV) — RO. This field indicates the version of the capability
structure.
Capability ID (CID) — RO. This field indicates this is capability for DMI.
Reserved
L1 Exit Latency (EL1) — L1 not supported on DMI.
L1 Exit Latency (EL1) — RO. This field is set to 010b to indicate an exit latency of
2 us to 4 us.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less
than 256 ns.
Active State Link PM Support (ASPM) — R/WO. This field indicates that L0s is
supported on DMI.
Active State Link PM Support (ASPM) — R/WO. This field indicates the level of active
state power management on DMI.
00 = Neither L0s nor L1s are supported
01 = L0s Entry supported on DMI
10 = L1 Entry supported on DMI
11 = Both L0s and L1 supported on DMI
Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.
Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.
00010006h
00012441h
Description
Description
Size:
Size:
Attribute:
Attribute:
Chipset Configuration Registers
Intel
RO
32-bit
RO/ R/WO
32-bit
®
ICH7 Family Datasheet