876784 Intel, 876784 Datasheet - Page 439

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.3.6
10.8.3.7
10.8.3.8
Intel
®
ICH7 Family Datasheet
LV2 — Level 2 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
NOTE: This register should not be used by Intel
LV3—Level 3 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
LV4—Level 4 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
7:0
7:0
7:0
Bit
Bit
Bit
logical processor, unless appropriate semaphoring software has been put in place to ensure
that all threads/processors are ready for the C2 state when the “read to this register”
instruction occurs.
LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and
LVL3 registers (which is not permitted), the Intel
read, and only perform a C2 transition.
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C3 state when the “read to this register”
instruction occurs.
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C4 state when the “read to this register”
instruction occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C3 power state” to the clock control logic. The C3 state
persists until a break event occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C4 power state” to the clock control logic. The C4 state
persists until a break event occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a level 2 power state” (C2) to the clock control logic. This will
cause the STPCLK# signal to go active, and stay active until a break event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
PMBASE + 15h (ACPI P_BLK + 5)
00h
No
PMBASE + 16h (ACPI P_BLK + 6)
00h
No
Description
Description
Description
®
iA64 processors or systems with more than 1
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
Power Well:
Attribute:
Size:
Usage:
Power Well:
®
ICH7-M/ICH7-U will ignore the LVL3
RO
8-bit
ACPI or Legacy
RO
8-bit
ACPI or Legacy
Core
RO
8-bit
ACPI or Legacy
Core
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