876784 Intel, 876784 Datasheet - Page 519

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.45
12.2
Table 12-2. Bus Master IDE I/O Register Address Map
Intel
®
ICH7 Family Datasheet
BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h
Default Value:
Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register,
located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
effect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. The description
of the I/O registers is shown in
31:0
Offset
Bits
BAR+
04–07
0Ch–
0Ah
0Bh
0Fh
10h
14h
00
01
02
03
08
09
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form
the contents of the third DWord of any BIST FIS initiated by the Intel
register is not port specific; its contents will be used for BIST FIS initiated on any port.
Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of
the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be
transmitted as the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated
in the BFCS register (D31:F2:E0h).
Mnemonic
BMIDP
BMICS
BMIDS
BMICP
BMISP
BMISS
AIDR
AIR
—
—
—
—
00000000h
–
EBh
Command Register Primary
Reserved
Bus Master IDE Status Register Primary
Reserved
Bus Master IDE Descriptor Table Pointer
Primary
Command Register Secondary
Reserved
Bus Master IDE Status Register Secondary
Reserved
Bus Master IDE Descriptor Table Pointer
Secondary
AHCI Index Register
AHCI Index Data Register
Table
12-2.
Register
Description
Attribute:
Size:
R/W
32 bits
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
00000000
Default
00h
00h
00h
00h
—
—
—
—
h
®
ICH7. This
R/W, RO
R/W, R/
WC, RO
R/W, R/
WC, RO
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
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