876784 Intel, 876784 Datasheet - Page 167

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.14.8.3
5.14.8.4
5.14.9
5.14.9.1
Note:
Table 5-34. Transitions Due to Power Button
Intel
®
ICH7 Family Datasheet
THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI
software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH7
starts throttling using the ratio in the THRM_DTY field.
When this bit is cleared the ICH7 stops throttling, unless the THTL_EN bit is set
(indicating that ACPI software is attempting throttling).
If both the THTL_EN and FORCE_THTL bits are set, then the ICH7 should use the duty
cycle defined by the THRM_DTY field, not the THTL_DTY field.
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH7 can be used to turn on/off
a fan.
Event Input Signals and Their Usage
The ICH7 has various input signals that trigger specific events. This section describes
those signals and how they should be used.
PWRBTN# (Power Button)
The ICH7 PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to Power Button Override
Function section below for further detail.
Present
S1–S5
S0–S4
State
S0/Cx
G3
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
PWRBTN# held low
for at least 4
consecutive seconds
Event
SMI# or SCI generated
(depending on SCI_EN)
Wake Event. Transitions to
S0 state
None
Unconditional transition to
S5 state
Transition/Action
Software typically initiates a
Sleep state
Standard wakeup
No effect since no power
Not latched nor detected
No dependence on processor
(e.g., Stop-Grant cycles) or
any other subsystem
Comment
Table
5-34.
167