876784 Intel, 876784 Datasheet - Page 45

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Introduction
Intel
®
ICH7 Family Datasheet
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile)
providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have
independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and
Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources.
The IDE interface integrates 16x32-bit buffers for optimal transfers.
The ICH7’s IDE system contains a single, independent IDE signal channel that can be
electrically isolated. There are integrated series resistors on the data and control lines
(see
Low Pin Count (LPC) Interface
The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the ICH7 resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.
Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA,
through the ICH7’s DMA controller. LPC DMA is handled through the use of the LDRQ#
lines from peripherals and special encoding on LAD[3:0] from the host. Single,
Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–
3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a
generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval timer. These three counters are combined
to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator
input provides the clock source for these three counters.
The ICH7 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the ICH7 supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt controller (PIC)
described in the previous section, the ICH7 incorporates the Advanced Programmable
Interrupt Controller (APIC).
Section 5.16
for details).
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