876784 Intel, 876784 Datasheet - Page 444

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.8.3.11
444
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits
are cleared by RTCRST#.
(Desktop
31:16
Only)
Bit
15
14
13
12
11
10
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16
Reserved
USB4_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS
PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
ICH7DH Only:
EL_SCI_EN — R/W. In Desktop Mode with Intel Quick Resume Technology feature
enabled, this bit enables the EL_SCI_STS signal to cause an SCI (depending on the
SCI_EN bit) when it is asserted.
In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit
will be treated as Reserved.
ICH7 and ICH7R Only:
Reserved
bit is set anytime USB UHCI controller #4 signals a wake event. Break events are
handled via the USB interrupt.
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
bit is set anytime USB UHCI controller #3 signals a wake event. Break events are
handled via the USB interrupt.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
00000000h
No
Bits 0–7, 9, 12, 14–31 Resume,
Bits 8, 10–11, 13 RTC
corresponds to GPIO0.
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W
32-bit
ACPI
®
ICH7 Family Datasheet