876784 Intel, 876784 Datasheet - Page 277

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.32
7.1.33
Intel
®
ICH7 Family Datasheet
LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value:
LSTS—Link Status Register
Offset Address: 01AA–01ABh
Default Value:
Desktop
Mobile/
Mobile
15:10
15:8
Ultra
Only
Only
6:2
1:0
1:0
9:4
3:0
Bit
Bit
7
Reserved
Extended Synch (ES) — R/W. When set, this bit forces extended transmission of
FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Mobile/
Ultra Mobile Only) at exit from L1 prior to entering L0.
Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s or L1 or both.
00 = Disabled
01 = L0s entry enabled
10 = L1 Entry enabled
11 = L0s and L1 Entry enabled
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Mobile/Ultra Mobile only: The ICH7 may also indicate x2 (000010b), depending on
(G)MCH configuration.
Link Speed (LS) — RO. Link is 2.5 Gb/s.
0000h
0041h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
16-bit
RO
16-bit
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