876784 Intel, 876784 Datasheet - Page 452
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876784
Manufacturer Part Number
876784
Description
Manufacturer
Intel
Datasheet
1.876784.pdf
(848 pages)
Specifications of 876784
Lead Free Status / RoHS Status
Compliant
- Current page: 452 of 848
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10.8.3.14
10.8.3.15
452
ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
ALT_GP_SMI_STS—Alternate GPI SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
15:0
15:0
Bit
Bit
Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding
GPIO to cause an SMI#. For these bits to have any effect, the following must be true.
NOTE: Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to
Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding
GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be
generated and the GPE0_STS bit set:
All bits are in the resume well. Default for these bits is dependent on the state of the
GPIO pins.
• The corresponding bit in the ALT_GP_SMI_EN register is set.
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
GPIO0.
PMBASE +38h
0000h
No
Resume
PMBASE +3Ah
0000h
No
Resume
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W
16-bit
ACPI or Legacy
R/WC
16-bit
ACPI or Legacy
®
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