876784 Intel, 876784 Datasheet - Page 280

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876784

Manufacturer Part Number
876784
Description
Manufacturer
Intel
Datasheet

Specifications of 876784

Lead Free Status / RoHS Status
Compliant
7.1.36
7.1.37
7.1.38
280
TRSR—Trap Status Register
Offset Address: 1E00–1E03h
Default Value:
TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h
Default Value:
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh
Default Value:
This register saves the data from I/O write cycles that are trapped for software to read.
63:25
23:20
19:16
63:32
31:4
15:2
31:0
3:0
1:0
Bit
Bit
Bit
24
Reserved
Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and
trapped). These bits are OR’ed together to create a single status bit in the Power
Management register space.
Note that the SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby
ensuring
completes. Each status bit is cleared by writing a 1 to the corresponding bit location
in this register.
Reserved
Read/Write# (RWI) — RO.
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
Reserved
Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables
associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the
trapped cycle.
Reserved
Reserved
Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined
after trapping a read cycle.
00000000h
0000000000000000h
0000000000000000h
that the processor can enter the SMI# handler when the instruction
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
Intel
R/WC, RO
32-bit
RO
64-bit
RO
64-bit
®
ICH7 Family Datasheet

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