876784 Intel, 876784 Datasheet - Page 187

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.16.2.4
Intel
®
ICH7 Family Datasheet
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following
steps are required:
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data
transfers terminate when the physical region described by the last PRD in the table has
been completely transferred. The active bit in the Status Register is reset and the
DDRQ signal is masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state)
when a terminal count condition exists; that is, the current region descriptor has the
EOL bit set and that region has been exhausted. The buffer is also flushed (write state)
or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register
is set. Software that reads the status register and finds the Error bit reset, and either
the Active bit reset or the Interrupt bit set, can be assured that all data destined for
system memory has been transferred and that data is valid in system memory.
Table 5-42
Register after a DMA transfer has started.
1. Software prepares a PRD table in system memory. The PRD table must be DWord-
2. Software provides the starting address of the PRD Table by loading the PRD Table
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the
7. At the end of the transfer, the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command
aligned and must not cross a 64-KB boundary.
Pointer Register. The direction of the data transfer is specified by setting the Read/
Write Control bit. The interrupt bit and Error bit in the Status register are cleared.
Command Register. The first entry in the PRD table is fetched and loaded into two
registers which are not visible by software, the Current Base and Current Count
registers. These registers hold the current value of the address and byte count
loaded from the PRD table. The value in these registers is only valid when there is
an active command to an IDE device.
IDE device. The IDE device and the host controller may or may not throttle the
transfer several times. When the last data transfer for a region has been completed
on the IDE interface, the next descriptor is fetched from the table. The descriptor
contents are loaded into the Current Base and Current Count registers.
register. It then reads the controller status followed by the drive status to
determine if the transfer completed successfully.
describes how to interpret the Interrupt and Active bits in the Status
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