876784 Intel, 876784 Datasheet - Page 584

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

14.1.2
14.1.3
584
DID—Device Identification Register (SMBUS—D31:F3)
Address:
Default Value:
PCICMD—PCI Command Register (SMBUS—D31:F3)
Address:
Default Value:
15:11
15:0
Bit
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Enables SERR# generation.
1 = Disables SERR# generation.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
0 = Disable
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Hardwired to 0.
Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address
Device ID — RO. This is a 16-bit value assigned to the Intel
Refer to the Intel
value of the Device ID Register.
Register.
02h
See bit description
04h
0000h
–
–
03h
05h
®
I/O Controller Hub 7 (ICH7) Family Specification Update for the
Description
Description
Attribute:
Size:
Attributes:
Size:
SMBus Controller Registers (D31:F3)
Intel
®
RO
16 bits
RO, R/W
16 bits
ICH7 SMBus controller.
®
ICH7 Family Datasheet