876784 Intel, 876784 Datasheet - Page 354

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

9.1.15
9.1.16
9.1.17
9.1.18
354
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh
Default Value:
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh
Default Value:
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h
Default Value:
INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch
Default Value:
31:0
31:0
15:8
7:0
7:0
Bit
Bit
Bit
Bit
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
as per the PCI bridge specification.
00000000h
00000000h
50h
0000h
–
3Dh
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
Intel
R/W
32 bits
R/W
32 bits
RO
8 bits
R/W, RO
16 bits
®
ICH7 Family Datasheet