876784 Intel, 876784 Datasheet - Page 589

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
Table 14-2. SMBus I/O Register Address Map
14.2.1
Intel
®
ICH7 Family Datasheet
HST_STS—Host Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 00h
RO
Default Value:
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a 0 to any bit position has no effect.
SMB_BASE
+ Offset
Bit
7
6
5
10h
11h
14h
16h
17h
0Fh
Byte Done Status (DS) — R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
NOTE: When the last byte of a block message is received, the host controller will set
INUSE_STS — R/WC (special). This bit is used as semaphore among various
independent software threads that may need to use the ICH7’s SMBus logic, and has no
other effect on hardware.
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will
SMBALERT_STS — R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only
If the signal is programmed as a GPIO, then this bit will not be set.
transmission of a byte (for Block Write commands) when the 32-byte buffer is not
being used. Note that this bit will be set, even on the last byte of the transfer. This
bit is not set when transmission is due to the LAN interface heartbeat.
reset the next read value to 0. Writing a 0 to this bit has no effect. Software can
poll this bit until it reads a 0, and will then own the usage of the host controller.
writing a 1 to it.
cleared by software writing a 1 to the bit position or by RSMRST# going low.
SMBUS_PIN_CTL
NOTIFY_DADDR
NOTIFY_DHIGH
this bit. However, it will not immediately set the INTR bit (bit 1 in this register).
When the interrupt handler clears the DS bit, the message is considered
complete, and the host controller will then set the INTR bit (and generate
another interrupt). Thus, for a block message of n bytes, the Intel
generate n+1 interrupts. The interrupt handler needs to be implemented to
handle these cases.
NOTIFY_DLOW
Mnemonic
00h
SLV_CMD
SLV_STS
SMBus Pin Control
Slave Status
Slave Command
Notify Device Address
Notify Data Low Byte
Notify Data High Byte
Register Name
Description
Attribute:
Size:
R/WC, R/WC (special),
8-bits
description
Default
register
See
00h
00h
00h
00h
00h
®
ICH7 will
R/W, RO
R/WC
Type
R/W
RO
RO
RO
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