876784 Intel, 876784 Datasheet - Page 360

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

9.1.23
360
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0)
Offset Address: 4Ch
Default Value:
31:14
13:8
4:3
Bit
7
6
5
2
1
0
Reserved
Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number
of PCI clocks after internally enqueuing an upstream memory read request at which
point the PCI target logic should insert wait states in order to optimize lead-off latency.
When the master returns after this threshold has been reached and data has not
arrived in the Delayed Transaction completion queue, then the PCI target logic will
insert wait states instead of immediately retrying the cycle. The PCI target logic will
insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or
STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived
yet).
Note that the starting event for this Read Latency Timer is not explicitly visible
externally.
A value of 0h disables this policy completely such that wait states will not be inserted
on the read lead-off data phase.
The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks
less than the typical idle lead-off latency expected for desktop Intel
This value may need to be changed by BIOS, depending on the platform.
Subtractive Decode Policy (SDP) — R/W.
0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any
1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the
NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.
PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR#
Assertion status bit (in the Bridge Proprietary Status register) will result in an internal
SERR# assertion on the primary side of the bridge (if also enabled by the SERR#
Enable bit in the primary Command register). SERR# is a source of NMI.
Secondary Discard Timer Testmode (SDTT) — R/W.
0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E,
1 = The secondary discard timer will expire after 128 PCI clocks.
Reserved
Peer Decode Enable (PDE) — R/W.
0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O
1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that
Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will
report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are
set, and CMD.SEE (D30:F0:04 bit 8) is set.
other device on the backbone (primary interface) to the PCI bus (secondary
interface).
corresponding Space Enable bit is set in the Command register.
bit 9)
cycles are not claimed.
falls outside of the memory and I/O window registers
00001200h
–
4Fh
Description
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
Intel
R/W, RO
32 bits
®
ICH7 Family Datasheet
®
ICH7 systems.