876784 Intel, 876784 Datasheet - Page 119

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.5.1.1
Table 5-5.
5.5.1.2
Table 5-6.
Intel
®
ICH7 Family Datasheet
LPC Cycle Types
The ICH7 implements the following cycle types as described in
LPC Cycle Types Supported
NOTES:
1.
Start Field Definition
Start Field Bit Definitions
NOTE: All other encodings are RESERVED.
Bits[3:0]
Encoding
Bus Master Write
Bus Master Read
0000
0010
0011
1111
(Desktop and
(Desktop and
Mobile Only)
Mobile Only)
Cycle Type
DMA Write
DMA Read
I/O Write
I/O Read
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0)
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a
target.
1 byte only. Intel
multiple 8-bit transfers.
1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple
8-bit transfers.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 1 below)
Can be 1, 2, or 4 bytes. (See Note 1 below)
Definition
®
ICH7 breaks up 16- and 32-bit processor cycles into
Comment
Table 5-5
119