876784 Intel, 876784 Datasheet - Page 126

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

5.6.3.1
Table 5-10. DMA Transfer Size
Note:
Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers
5.6.4
5.6.5
126
Address Shifting When Programmed for 16-Bit I/O Count by Words
The ICH7 maintains compatibility with the implementation of the DMA in the PC AT that
used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device
count-by-words.
The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
The address shifting is shown in
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following TC. The Base Registers are loaded simultaneously
with the Current Registers by the microprocessor when the DMA channel is
programmed and remain unchanged throughout the DMA service. The mask bit is not
set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ
is detected.
Software Commands
There are three additional special software commands that the DMA controller can
execute. The three software commands are:
They do not depend on any specific bit pattern on the data bus.
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words (Address
Shifted)
DMA Device Date Size And Word Count
• Clear Byte Pointer Flip-Flop
• Master Clear
• Clear Mask Register
Address
A[23:17]
A[16:1]
Output
A0
8-Bit I/O Programmed
Table
Address (Ch 0–3)
5-11.
A[23:17]
A[16:1]
A0
Current Byte/Word
Count Register
Words
Bytes
16-Bit I/O Programmed
Intel
Address (Ch 5–7)
®
ICH7 Family Datasheet
Current Address
Functional Description
(Shifted)
A[23:17]
A[15:0]
Increment/
Decrement
0
1
1