876784 Intel, 876784 Datasheet - Page 259

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Register and Memory Mapping
Table 6-3.
6.4
Table 6-4.
Intel
®
ICH7 Family Datasheet
Variable I/O Decode Ranges
NOTE:
1.
Memory Map
Table 6-4
decodes. Cycles that arrive from DMI that are not directed to any of the internal
memory targets that decode directly from DMI will be driven out on PCI unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH7 may then
claim the cycle for the internal LAN controller.
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the ICH7’s memory-
mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which
means potential deadlock conditions may occur.
Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
LAN
LPC Generic 1
LPC Generic 2
LPC Generic 3
LPC Generic 4
I/O Trapping Ranges
0000 0000h–000D FFFFh
0010 0000h–TOM
000E 0000h–000E FFFFh
000F 0000h–000F FFFFh
FEC0 0000h–FEC0 0100h
FED4 0000h–FED4 0FFFh
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
(Top of Memory)
Memory Range
Decode range size determined by D31:F0:ADh:bits 5:4
Range Name
shows (from the processor perspective) the memory ranges that the ICH7
1
Firmware Hub (or
Firmware Hub (or
I/O APIC inside
Anywhere in 64 KB I/O
Space
Firmware Hub
Firmware Hub
Main Memory
Intel
TPM on LPC
Anywhere in 64 KB I/O
Anywhere in 64 KB I/O
Anywhere in 64 KB I/O
Anywhere in 64 KB I/O
Anywhere in 64 KB I/O
Target
PCI)
PCI)
®
Mappable
ICH7
1
1
Space
Space
Space
Space
Space
TOM registers in Host controller
Bit 6 in Firmware Hub Decode Enable register
is set
Bit 7 in Firmware Hub Decode Enable register
is set
Bit 8 in Firmware Hub Decode Enable register
is set
Bit 9 in Firmware Hub Decode Enable register
is set
Dependency/Comments
4 to 256
4 to 256
4 to 256
4 to 256
1 to 256
(Bytes)
Size
64
Trap on Backbone
LPC Peripheral
LPC Peripheral
LPC Peripheral
LPC Peripheral
LAN Unit
Target
259