876784 Intel, 876784 Datasheet - Page 419

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.1.1
Intel
®
ICH7 Family Datasheet
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0h
Default Value:
Lockable:
(Desktop
(Desktop
(Desktop
(Desktop
(Mobile/
(Mobile/
Mobile
Mobile
Mobile
Mobile
15:11
(Ultra
Only)
Only)
Only)
Only)
Only)
Only)
Only)
Ultra
Ultra
and
3:2
Bit
10
10
9
8
7
7
6
5
5
4
Reserved
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to
1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to go
Reserved
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved
Reserved
Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when
software does a LVL3 read, the Intel
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,
not an IA_32 processor. This may be used in various state machines where there are
behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the
Reserved
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE +
30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by
PLTRST#).
Reserved
go active.
active.
processor power.
0000h
No
Description
®
Attribute:
Size:
Usage:
Power Well:
ICH7-M/ICH7-U transitions to the C4 state.
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
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