EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1069
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 3: ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
Dynamic Reconfiguration
Table 3–4. MegaWizard Plug-In Manager Options (Page 6)
February 2011 Altera Corporation
Enable illegal mode
checking
Enable self recovery
Use rate_switch_out
port to read out the
current data rate division
Use the
rx_tx_duplex_sel
port to enable RX only,
TX only or duplex
configuration
ALTGX_RECONFIG
Setting
Table 3–4
your ALTGX_RECONFIG custom megafunction variation.
Make your selections on page 6, then click Next.
When you select this option, the ALTGX_RECONFIG
MegaWizard Plug-In Manager provides the error output
port. The dynamic reconfiguration controller detects the
error conditions within two reconfig_clk cycles,
de-asserts the busy signal, and asserts the error signal for
two reconfig_clk cycles.
When you select this option, the controller automatically
recovers if the operation did not complete within the
expected time. The error signal is driven high whenever the
controller performs a self recovery.
The rate_switch_out[1:0] signal is available when you
select Data Rate Division in TX mode. You can read the
existing local divider settings of a transmitter channel at
this port. The decoding for this signal is listed below:
2’b00—Division of 1
2’b01—Division of 2
2’b10—Division of 4
2’b11—Not supported
You can read or write the receiver and transmitter settings,
only the receiver settings, or only the transmitter settings,
based on the value you set at the
rx_tx_duplex_sel[1:0] port;
■
■
■
■
If you disable the rx_tx_duplex_sel[1:0] port, the
dynamic reconfiguration controller reads or writes both the
receiver and transmitter settings.
2’b00—Duplex mode
2’b01—RX only mode
2’b10—TX only mode
2’b11—unsupported value (do not use this value)
lists the available options on page 6 of the MegaWizard Plug-In Manager for
Description
“Error Indication During Dynamic
Reconfiguration” section of the
Dynamic Reconfiguration in
Stratix IV Devices
“Error Indication During Dynamic
Reconfiguration” section of the
Dynamic Reconfiguration in
Stratix IV Devices
“Data Rate Division in Transmitter
Mode Details” mode section in the
Dynamic Reconfiguration in
Stratix IV Devices
“Dynamically Reconfiguring PMA
Controls” section of the
Reconfiguration in Stratix IV
Devices
Stratix IV Device Handbook Volume 3
chapter.
Reference
chapter.
chapter.
chapter.
Dynamic
3–13
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