EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 541
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–85. Byte Ordering in Single-Width Modes
February 2011 Altera Corporation
tx_datain[15:8]
tx_datain[7:0]
1
D2
D1
D3
A
The byte ordering block modes of operation in both single-width and double-width
modes are:
■
■
In word-alignment-based byte ordering, the byte ordering block starts looking for the
byte ordering pattern in the byte-deserialized data every time it sees a rising edge on
the rx_syncstatus signal. After a rising edge on the rx_syncstatus signal, if the byte
ordering block finds the first data byte that matches the programmed byte ordering
pattern in the MSByte position of the byte-deserialized data, it inserts one
programmed PAD pattern to push the byte ordering pattern in the LSByte position. If
the byte ordering block finds the first data byte that matches the programmed byte
ordering pattern in the LSByte position of the byte-deserialized data, it considers the
data to be byte ordered and does not insert any PAD pattern. In either case, the byte
ordering block asserts the rx_byteorderalignstatus signal.
You can choose word-alignment-based byte ordering in the Rate match/Byte order
tab of the ALTGX MegaWizard Plug-In Manager. For the What do you want the byte
ordering to be based on? question, select the The sync status signal from the word
aligner option.
Figure 1–85
In this example, A is the programmed byte ordering pattern and PAD is the
programmed PAD pattern. The byte deserialized data places the byte ordering pattern
A in the MSByte position, resulting in incorrect byte ordering. Assuming that a rising
edge on the rx_syncstatus signal had occurred before the byte ordering block sees
the byte ordering pattern A in the MSByte position, the byte ordering block inserts a
PAD byte and pushes the byte ordering pattern A in the LSByte position. The data at
the output of the byte ordering block has correct byte ordering as reflected on the
rx_byteorderalignstatus signal.
D4
Transmitter
D5
Word-alignment-based byte ordering
User-controlled byte ordering
Word-Alignment-Based Byte Ordering
Serializer
Byte
shows an example of the byte ordering operation in single-width modes.
Channel
Deserializer
Byte
Receiver
D1
xx
D2
A
D4
D3
rx_byteorderalignstatus
Ordering
Byte
Stratix IV Device Handbook Volume 2: Transceivers
D1
xx
PAD
D2
D3
A
D5
D4
rx_dataout[15:8]
rx_dataout[7:0]
1–97
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