EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 454

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–10
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–5
the EP4S40G2F40 Stratix IV GT devices.
Figure 1–5. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S40G2F40
Stratix IV GT Devices
Notes to
(1) EP4S40G2F40ES1 devices do not have 10G auxiliary transmit (ATX) PLL blocks. Use the CMU PLL to generate
(2) If you are using the PCIe hard IP block, the EP4S40G2F40 device is not able to migrate to the EP4S40G5H40 device.
transceiver clocks for channels configured at 11.3 Gbps.
EP4S40G2F40
Figure
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
shows the transceiver channel, PLL, and PCIe hard IP block locations for
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
CMU Channel 1
CMU Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
ATX PLL (6G)
8G Channel 3
8G Channel 2
1–5:
(Note
1),
(2)
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
10G Channel 3
10G Channel 2
Transceiver Channel Locations
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
8G Channel 1
8G Channel 0
8G Channel 3
8G Channel 2
ATX PLL (6G)