EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 791

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
Table 3–12. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct) Configuration Using CMU PLL
for Example 9
February 2011 Altera Corporation
inst0
inst1
Instance Name
User Defined
Number of Channels
Key Observations
■
■
Combining Channels Configured in Basic (PMA Direct) ×N Configuration with Non-Basic
(PMA Direct) Configurations
The Quartus II software only allows a combination of a transceiver channel instances
configured in Basic (PMA Direct) ×N mode with instances in non-Basic (PMA Direct)
configurations; for example, GIGE and SDI.
Consider the example design listed in
combining a Basic (PMA Direct) ×N configuration with a non-Basic (PMA Direct)
configuration using a CMU PLL.
Note that channel 5 in inst0 is placed in transceiver block 1 and receives the
high-speed clock through the ×N_Top clock line.
Some of the channels in transceiver block 1 receive their high-speed clock from the
×N_Bottom clock line. Because the ×N_Top and ×N_Bottom lines are separate, this
scenario is allowed. To understand the clock multiplexer on the ×N clock lines,
refer to
Example 9
9
1
Figure 3–18 on page
Effective Data Rate (Gbps)
1.25
1.5
3–34.
Table 3–12
Configuration
Receiver and
Receiver and
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter
Transmitter
for the two instances when
Basic (PMA Direct) ×N
Functional Mode
GIGE
3–37