EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 76
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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3–20
Stratix IV Device Handbook Volume 1
f
Figure 3–18
behavior in old data mode for M9K and M144K blocks.
Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock.
In this mode, you also have two output choices: “old data” or “don’t care”. In old data
mode, a read-during-write operation to different ports causes the RAM outputs to
reflect the “old data” at that address location. In don’t care mode, the same operation
results in a “don’t care” or “unknown” value on the RAM outputs.
Read-during-write behavior is controlled with the RAM MegaWizard Plug-In
Manager. For more information, refer to the
Guide.
Figure 3–19
behavior for old data mode in MLABs.
Figure 3–19. MLABs Mixed-Port Read-During-Write: Old Data Mode
q_b(registered)
q_a (asyn)
wraddress
rdaddress
byteena_a
address
bytenna
data_in
data_a
wrena
wrena
clk_a
rdena
clk_a
shows sample functional waveforms of same-port read-during-write
shows a sample functional waveform of mixed-port read-during-write
AAAA
11
A123
01
A0 (old data)
A0 (old data)
A0
A0
BBBB
01
B456
10
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
A0
D
old
D
old
AAAA
CCCC
10
23
C789
00
Internal Memory (RAM and ROM) User
B423
AABB
DDDD
11
DDDD
A1(old data)
A1(old data)
EEEE
A1
A1
01
February 2011 Altera Corporation
A1
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11
DDDD
DDDD
FFFF
10
Design Considerations
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