EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 848
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
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5–2
Table 5–1. Glossary of Terms Used in this Chapter (Part 2 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Alternate CMU Transmitter
PLL
Channel and Transmitter PLL
Select/reconfig Mode
Logical Channel Addressing
Logical Reference Index
Logical tx pll
Main PLL
Memory Initialization File,
also known as .mif
PMA Controls
PMA-Only Channels
Regular Transceiver Channel
Term
Refers to one of the two CMU PLLs within a transceiver block.
Refers to the following dynamic reconfiguration modes:
■
■
■
■
Used whenever the concept of logical channel addressing is explained. This term does not
refer to the logical_channel_address port available in the ALTGX_RECONFIG
MegaWizard Plug-In Manager.
Refers to the logical identification value that you must set up for the transmitter PLLs used
in the design. You can use a set up value of 0, 1, 2 or 3 in the Reconfiguration Settings
screen of the ALTGX MegaWizard Plug-In Manager.
Refers to the logical reference index value of the transmitter PLLs stored in the memory
initialization file (.mif).
Refers to the transmitter PLL configured in the General screen of the ALTGX MegaWizard
Plug-In Manager.
When you enable .mif generation in your design, a file with the .mif extension is generated.
This file contains information about the various ALTGX MegaWizard Plug-In Manager
options that you set. Each word in the .mif is 16 bits wide. The dynamic reconfiguration
controller writes information from the .mif into the transceiver channel, but only when you
use a reconfiguration mode that supports .mif-based reconfiguration.
Represents analog controls (Voltage Output Differential [V
Manual Equalization) as displayed in both the ALTGX and ALTGX_RECONFIG MegaWizard
Plug-In Managers.
Channels configured in Basic (PMA Direct) functional mode.
Refers to a transmitter channel, a receiver channel, or a duplex channel that has both PMA
and physical coding sublayer (PCS) blocks.
CMU PLL reconfiguration
Channel and CMU PLL reconfiguration
Channel reconfiguration with transmitter PLL select
Central control unit reconfiguration
Description
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
OD
], Pre-emphasis, and
February 2011 Altera Corporation
Glossary of Terms
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