EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 773
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Channels Configured in Protocol Functional Modes
Figure 3–8. Basic ×4 Functional Mode Configuration when Combining Channels
Notes to
(1) You can configure this channel in Basic (PMA Direct) single-width or double-width mode.
(2) You can configure this channel only in Basic (PMA Direct) single-width mode.
(3) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents the ×N bottom clock line.
(4) To simplify the illustration, only the transmitter side is shown. PCIe ×4 refers to PCIe with the sub protocol set to Gen1 x4 and Gen2 x4.
February 2011 Altera Corporation
Figure
3–8:
(Basic [PMA Direct] xN mdoe) (2)
4. Using the receiver side of the CMU channels depends on whether you use
5. If you use ATX PLL to generate clocks for the ×4 bonded functional mode, you can
Figure 3–8
transceiver block are used.
CMU1 PLL or CMU0 PLL to generate clocks for the bonded ×4 functional mode. If the
CMU PLL within the corresponding CMU channel is not available to perform
CDR functionality, you cannot configure it as a receiver.
use both the Transmitter and Receiver side of the CMU0 and CMU1 channels. You
must satisfy the requirements specified in number 3.
1
Figure 3–8
(PMA Direct) xN mode within the same transceiver block.
TX - Basic
For XAUI, the option to select ATX PLL is not available.
shows a configuration in which all the transmitter channels in the
CMU0 Channel
shows the combination of Basic/PCIe x4 functional mode with Basic
ATX PLL
TX2 - Basic x4/
TX3 - Basic x4/
(PMA Direct xN mode) (1)
TX1 - Basic x4/
ATX PLL
TX0 - Basic x4/
PCIe x4
PCIe x4
PCIe x4
PCIe x4
CMU1 Channel
Central Clock
Divider
x4 Clock Line (3)
xN Top Clock Line (3)
Stratix IV Device Handbook Volume 2: Transceivers
(Note 4)
xN Bottom Clock Line
3–19
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