EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 548

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–104
Stratix IV Device Handbook Volume 2: Transceivers
f
1
The /N divider receives the high-speed clock output from one of the CMU PLLs and
produces a high-speed serial clock. Use this clock for bonded functional modes such
as Basic ×4/×8, XAUI, and PCIe ×4/×8 configurations. In XAUI and Basic ×4/×8
modes, the Quartus II software chooses the path (shown by “1” in the MUX) and
provides the high-speed serial clock to all the transmitter channels within the
transceiver block.
■
■
■
For more information about the clock from the master transceiver block, refer to the
Transceiver Clocking in Stratix IV Devices
The PCIE rateswitch circuit is enabled only in PCIe ×4 mode. In PCIe ×8 mode, the
PCIE rateswitch circuit of the CMU0 clock divider of the master transceiver block is
active.
There are two paths in the PCIE rateswitch circuit. One path divides the /N output by
two. The other path forwards the /N divider output.
■
■
The PCIE rateswitch circuit performs the rateswitch operation only for the transmitter
channels. For the receiver channels, the rateswitch circuit within the receiver CDR
performs the rateswitch operation.
The PCIE rateswitch circuit is controlled by the PCIe rateswitch controller in the CCU.
The PCIe rateswitch controller asserts the pipephydonestatus signal for one clock
cycle after the rateswitch operation is completed for both the transmit and receive
channels.
For more information about PCIe functional mode rate switching, refer to
(5 Gbps) Support” on page
In PCIe ×4 mode, the clock path through the PCIe rateswitch circuit block is
selected. This high-speed serial clock is provided to all the transmitter channels.
In PCIe ×8 mode and Basic ×8 mode, only the CMU0 clock divider of the master
transceiver block provides the high-speed serial clock to all eight channels.
In PCIe ×1 mode, the CMU0 clock divider does not provide a high-speed serial
clock. Instead, the local clock divider block in the transmitter channel receives the
CMU0 or CMU1 PLL high-speed clock output and generates the high-speed serial
clock to its serializer.
When you set the rateswitch port to 0, the PCIe rateswitch controller (in the CCU)
signals the PCIE rateswitch circuit to select the divide by /2 to provide a
high-speed serial clock for the Gen1 (2.5 Gbps) data rate.
When you set the rateswitch port to 1, the /N divider output is forwarded,
providing a high-speed serial clock for the Gen2 (5 Gbps) data rate to the
transmitter channels.
High-Speed Serial Clock Generation
PCIE Rateswitch Circuit
Figure 1–91
shows the timing diagram for the rateswitch operation.
1–140.
chapter.
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture
“PCIe Gen2